1. Field of the Invention
This invention relates to a system for detecting faults associated with a logic circuit and more particularly to a system in which serial data shift registers are interfaced to the logic circuit such that substantially all of the propagations delay errors associated with the circuit are detected at the approximate operational speed of the circuit.
2. Discussion
In general, propagation delay faults associated with a logic circuit usually result in the production of an error in the logic circuit's output signal. This output error is usually due to delays in the propagation of signals through the constituent elements and signal paths of the logic circuit. Propagation-delay-type faults may drastically reduce the operational capability of a logic circuit. Additionally, propagation delay faults are usually particularly difficult to isolate during the actual operation of the logic circuit. This difficulty in detection is due to the fact that in actual logic circuit operation the fault detector is left to probe manually in an environment in which the failure condition may be difficult to replicate, such as with faults which are associated with temperature or low supply voltage.
To effectively test for propagation delay faults, it is necessary to test several of the most critical signal paths within the logic circuit. This testing should be done at the approximate operational speed of the logic circuit. Testing at lower speeds might result in the "masking" of some propagation delay faults. That is, excessive propagation delay might not become evident at speeds which are slower than that of the logic circuit's normal operation.